1. Field
This document relates to method of forming a low-resistance wire and a method of manufacturing a thin film transistor using the same, and more particularly, to a method of forming low-resistance metal gate and data wirings and a method of manufacturing a thin film transistor using the same.
2. Discussion of the Related Art
Various flat panel displays having reduced weight and volume when compared with a cathode ray tube have been developed. Flat panel displays (FPDs) include liquid crystal displays (LCD), field emission displays (FED), plasma display panels (PDP), organic light emitting diode (OLED) displays, and the like.
Out of the flat panel displays, the application range of the liquid crystal displays has widened because the liquid crystal display can be manufactured to be lightweight and thin and can be driven under low power consumption. Moreover, the OLED displays have a fast response time equal to or less than about 1 ms, low power consumption, and a wide viewing angle by a self light emitting. Thus, the OLED displays have been considered as a next generation display.
The liquid crystal displays and the OLED displays are driven by a passive matrix method or an active matrix method using a thin film transistor. The active matrix method, in which a thin film transistor and a pixel electrode connected to the thin film transistor are arranged in a matrix, are attracting considerable attention due to its high resolution and superior moving picture reproducing capability.
An active matrix display using a thin film transistor supplies signals to each pixel through gate wirings for supplying scan signals and data wirings for supplying data signals, and supplies power to each pixel through power lines for supplying power.
For a large-sized display device of more than 18 inches having a high resolution, the material used for the gate and data wirings becomes a highly important factor for determining picture quality because the picture quality depends on the specific resistance of the material. The resistance of the entire lines including the gate wirings and the data wirings increases with the trend of large-sized and high-resolution displays. This increases the resistance of each line and the parasitic capacitance between the lines, thus leading to an RC delay caused by resistance-capacitance. Moreover, crosstalk occurs due to the RC-delay, thereby deteriorating picture quality.
Therefore, low-resistance metals such as aluminum or aluminum alloys may be used for the gate wirings and the data wirings in order to prevent such an RC-delay. However, aluminum has poor chemical corrosion resistance, and may cause a defect in a subsequent process.
To solve this problem, the line width or the line thickness may be increased to reduce resistance. However, increasing the line thickness may increase the risk of short-circuiting due to a large step coverage.
Hereinafter, the above-described problem will be explained in more detail with reference to FIGS. 1a to 1e. FIGS. 1A to 1E are cross-sectional views showing a method of manufacturing a thin film transistor used for a related art active matrix display.
Referring to FIG. 1A, a gate metal film is deposited on a substrate 10 and patterned to form a gate wiring (not shown) and a gate electrode 20 extending from the gate wiring.
Referring to FIG. 1B, a gate insulating film 30, an amorphous silicon film 32, and an impurity-containing amorphous silicon film 34 are sequentially deposited over the entire surface of the substrate 10 with the gate electrode 20 formed thereon so as to cover the gate electrode 20. The amorphous silicon film 32 and the impurity-containing amorphous silicon film 34 are patterned to form an active layer 35.
Referring to FIG. 1C, a data metal layer is deposited over the entire surface of the substrate 10 with the active layer 35 formed thereon. The data metal layer is patterned to form a data wiring (not shown) crossing the gate wiring, with the gate insulating film 30 interposed therebetween, and a source electrode 42 and a drain electrode 44 on the active layer 35 so as to partially overlap with the gate electrode 20 and face each other. Next, an impurity-containing amorphous silicon pattern exposed between the source electrode 42 and the drain electrode 44 is etched using the source electrode 42 and the drain electrode 44 as a mask, thereby forming a channel Ch.
Referring to FIG. 1D, a passivation film 50 is formed over the entire surface of the substrate 10 with the data wiring (not shown), the source electrode 42, and the drain electrode 44 formed thereon, and then a contact hole 52 is formed to expose a portion of the drain electrode 44 of the thin film transistor. The passivation film 50 is for protecting the channel Ch from external moisture or contact.
Referring to FIG. 1E, a transparent metal layer is deposited on the passivation film 50 with the contact hole formed therein, and then patterned to form a pixel electrode 60. The pixel electrode 60 is connected to the drain electrode 44 of the thin film transistor exposed through the contact hole 52 of the passivation film 50.
FIG. 2 is an enlarged cross-sectional view showing portion A of FIG. 1e. Referring to FIG. 2, the gate electrode 20, the source electrode 42, and the drain electrode 44 are protruded higher than their neighboring parts because they are formed by patterning. Accordingly, when the source electrode 42 and the pixel electrode 60 are formed thick to decrease electrical resistance, short-circuiting may occur because the step coverage of the gate insulating film 30, active layer 35, source electrode 42, and drain electrode 44 to be formed during a subsequent process increases because of the step difference with the gate electrode. Also, when the source electrode 42 and the drain electrode 44 are likewise formed thick to decrease electrical resistance, short-circuiting may occur because the step coverage of the passivation film 50 and the pixel electrode 60 to be formed during a subsequent process increases because of the step difference with the source electrode and the drain electrode.
Moreover, as shown in FIG. 2, the parasitic capacitance Cp between the gate electrode 20 and the source and drain electrodes 42 and 44 may increase due to the step difference with the gate electrode 20. This may cause severe flickering on the display device and generate a picture quality defect.